TSMC and Cadence develop wafer stacking method

TSMC, recently the world’s largest chip manufacturer, has developed a new method of packaging chips. The new Wafer-on-Wafer technique stacks dies, or chips, on top of each other at the wafer level.

Chip manufacturers are continuously looking for more computing power in increasingly smaller surfaces. With memory such as RAM and NAND, layers have been stacked on top of each other for a long time and connected to each other with so-called TSVs. Die-through silicon vias are metal connections that are made through extremely small holes in a die, or a piece of silicon. Electrical signals can connect chips to each other through those metal posts.

TSMC already has two techniques for making such 2.5 and 3D packages of several dies in one chip. The first is a technique called chip on wafer on substrate that connects several dies with an interposer. The second is TSMC’s take on fanout wafer-level packaging called Integrated Fanout by the company, which connects chips in epoxy, without interposer or TSVs.

A third 3D packaging method has been added, which is called Wafer-on-Wafer. Two wafers are glued on top of each other, whereby the metal interconnect layer of one chip is directly connected to the same layer of the inverted wafer on top. Because that beol layer, the metal layer with interconnects, also provides the contact points to connect the chip, TSVs are used to carry that i/o out. The TSVs are placed in the top chip, which becomes the bottom after flipping, during chip production.

Because the dies are connected at the wafer level, there is no option to exclude broken dies from the wow process. That is why TSMC will only use the technique for productions with a high yield, because otherwise too many good dies would be lost if they are linked to a broken one. The technique does not have to be limited to linking two wafers, but can stack several wafers on top of each other, provided that the underlying wafers always receive TSVs to communicate with each other.

Cadence’s role in this technology, which TSMC has not yet announced, but has been explained at Cadence, is that of supplier of chip design tools and packaging tools. Such tools are needed both during chip design and packaging the die into a functional chip, and companies such as Cadence work closely with chip products.