Toshiba investigates flash memory with five bits per cell

Toshiba has started researching PLC nand memory, flash memory that stores five bits per cell. The company has gotten a modified version of its qlc-nand to work as plc-nand. However, there are still many challenges.

In order for plc-nand to work, the memory cells must be able to store 32 different voltage levels. With qlc- and tlc-nand this is 16 and 8 respectively. The high number of voltage levels must also be accurately read by an SSD controller. This required accuracy is a major challenge when making PLC memory. It is not yet clear whether and when PLC Nand memory will actually be used in products.

With the use of five bits per cell, the data density of flash memory can be further improved, but the speed and lifespan are reduced compared to variants with fewer bits per cell. This is already the case with the qlc-nand with four bits per cell, which is currently used by some SSD manufacturers.

According to Tom’s Hardware, which attended a presentation from Toshiba, new features of the nvme protocol should compensate for the shorter lifespan and slower speed of plc-nand. For example, the Zoned Namespaces technique should reduce the required write amplification and over-provision. Also, ZNS must limit the amount of dram required from a controller.

Toshiba is also working on new ways to further improve flash memory density. The memory manufacturer showed a way to cut memory cells in half, as it were. However, the manufacturer does not yet know whether this is a feasible method.

Furthermore, during his presentation, Toshiba showed a timeline with successors to its BiCS flash memory. Eventually, the speed will reach 2000MT/s with the seventh generation, which will use the pci-e 6.0 protocol.