Toshiba introduces 64-core SOC

Toshiba has announced the development of a 64-core soc for embedded applications. The 40nm chip is made up of two clusters of 32 cores and has dedicated hardware for image processing on board.

The New Toshiba Soc is becoming produced on a 40nm LP process with eight copper layers for the interconnect. The chip has a total surface area of ​​210mm², while the two 32core clusters each occupy 42mm². The clock speed of the clusters is set at 333MHz, with which a total of 1.5Tops can be calculated. This is fourteen times the octocore soc that Toshiba first announced at the ISSCC 2008 trade show. That chip used a 65nm process.

In addition to using a smaller process, Toshiba has kept the power consumption of the 64core soc low in other ways. For example, unused parts of the chip can be deactivated and Toshiba uses its own, energy-efficient data-mapping flip-flop circuit. The chip is also equipped with hardware to speed up the playback of video content. Decoding an h264-1080/30p movie would therefore only consume 500mW of power. Communication between the cores uses network on a chip-technology.

Toshiba wants to use the new ‘many-core’ SOC for the automotive industry, but also for consumer products. To do this, Toshiba has integrated special image recognition hardware on the chip. Also can the chip can process 4k2k video content at a frame rate of 15fps using less than 800mW. Toshiba will provide more details about the chip at the 2012 IEEE Symposia on VLSI Technology and Circuits, which took place June 12-14 in Honolulu.