Samsung validates sram made with euv on 7nm

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Samsung has ready 256Mbit SRAM that is produced at 7nm with EUV technology. According to Samsung itself, the working chip has increased its confidence in EUV as the successor to immersion lithography.

Samsung used euv in four of the six layers in the validated design of the SRAM. The company announced the progress at the International Solid-State Circuits Conference, which will take place in San Francisco until February 15. In November of last year, Samsung already announced that it would achieve a yield of eighty percent for the EUV production of 256Mbit SRAM.

Compared to then, not only the correct operation has been validated, but the size of the bit cell has also been reduced, from 0.027 to 0.026 µm², writes the German All Electronics. It concerns the surface of a 6T sram cell, consisting of six transistors. The caches of processors consist of this static ram. The company did not say whether Samsung can also mass-produce the chips. “Having real, working silicon took our worries away,” is all one employee told EETimes about it.

Samsung and GlobalFoundries in particular are committed to a rapid introduction of euv. The manufacturers want to switch to euv to be able to apply smaller structures on the silicon cost-effectively. The use of the current 193nm immersion lithography from 7nm becomes too expensive and time-consuming. Intel and TSMC are more cautious and think it will be years before the euv technology can be used for mass production. Intel takes a backlog in the reduction of chip features for granted. During ISSCC, Intel announced that it had made sram bit cells with a size of 0.0312 µm² and 0.0367 µm² at 10nm.

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