Samsung starts production of 96-layer 3d-nand

Samsung has started mass production of the fifth generation of its 3d-v-nand memory. This new memory consists of at least more than 90 layers of memory cells and is accompanied by a new interface, relatively less power consumption and lower latency.

According to the manufacturer, a new, so-called ‘toggle DDR 4.0 interface’ is used. This allows the 256GB-v-nand to achieve a data rate of 1.4Gbit/s, which is a 40 percent improvement over the predecessor with 64-layer 3d-nand. Furthermore, the voltage has been reduced from 1.8 to 1.2V, which compensates for the energy consumption for the faster interface. The total energy consumption is therefore comparable to the 64-layer chip.

Samsung initially manufactures the new memory in the form of tlc-dies with a capacity of 256Gbit. Larger dies are to follow later, including 1Tb-qlc-nand where each cell consists of four bits. With the new memory, the write speed is 500 microseconds, a 30 percent improvement; the manufacturer has reduced the response time required for reading to 50 microseconds.

The manufacturer does not provide much information about the production process, but does report that the height of each layer of a memory cell has been reduced by 20 percent. According to Samsung, this contributes to better efficiency of data processing, among other things. Manufacturing productivity is also said to have improved by more than 30 percent.