Leaked AMD Zen 5 slides show IPC improvements of ten to fifteen percent

YouTuber Moore’s Law Is Dead has shown two alleged slides from an internal AMD presentation containing information about the Zen 5 architecture. It is said to have an IPC improvement of ten to fifteen percent compared to Zen 4. The L1 cache is also larger at 48KB.

The images have appeared in a video from Moore’s Law Is Dead, although it is not known where the images come from and what their authenticity is. If the slides, which appear to come from an AMD presentation, are legitimate, much more information is known about the company’s upcoming architecture. That is the Zen 5 architecture for 4nm and 3nm chips, which is codenamed Nirvana and is intended for the future Ryzen 8000 CPUs.

The slides show that the Zen 5 chips have an improvement in instructions per clock cycle, or ipc, of between ten and fifteen percent. The slide also states that the Zen 5 chips have an L1D cache of 48KB, an improvement compared to the 32KB that the current Zen 4 generation has. The number of cores per ccx, or core complexes, doubles; that goes from eight in the current generation to sixteen. Further information concerns the number of wide dispatches, of which Zen 5 will receive eight, and the CPUs will also receive six aluminum and ‘FP-512 variants’.

The slides also contain information about the even newer Zen 6 architecture. It will be codenamed Morpheus and would once again have an IPC improvement of ten percent compared to Zen 5 and a 32-core ccx.