Intel wants to put together chip packages more flexibly with combination emib and Foveros

Intel will combine its emib and Foveros technologies to be able to put together chip packages more flexibly. In addition, the company will deploy larger through silicon vias for vertical stacking.

Intel announced new technologies for flexible assembly of chip packages at the SemiconWest conference in San Francisco. According to the manufacturer, the role of the package is somewhat underexposed, but its importance is increasing. A package can contain various chiplets, I/O parts and other components, and contains the important connection to the motherboard.

As chip manufacturers find it more difficult to further reduce chip structures, they have to rely more on improvements to the architecture, and the combination of chiplets and packaging. With regard to the latter, Intel announces that it will apply the techniques co-emib, omni-directional interconnect and mdio.

Co-emib is the combination of emib, or embedded interconnect bridge, with Foveros. Emib is Intel’s technique for connecting chip components on a substrate with high-bandwidth embedded silicon ‘bridges’ instead of a large silicon interconnect. The technology enables the company to assemble chips like blocks of blocks. Intel already uses emib to connect FPGAs to memory and with Kaby Lake-G processors to let the Radeon GPU communicate with hbm.

Foveros is the name Intel gives to stacking chips and connecting them with vertical TSV channels, or through silicon vias. The bottom layer is the I/O interposer that communicates through the TSVs with processor and memory dies on top of it. Intel has demonstrated the use of Foveros with a Lakefield chip, combining four frugal Atom cores with a powerful Sunny Cove core at 10nm with an interposer at 22nm. As with emib, one of the advantages of Foveros is the ability to combine chip parts made on different production processes.

With co-emib, Intel combines emib with two or more Foveros elements to provide ‘virtually a single chip’ performance. According to Intel, the combination can also connect memory and other high-bandwidth blocks.

As an extension of that, there is the odi, or omni-directional interconnect. This new interconnect makes it possible to connect chiplets horizontally, but can also be used vertically, with a higher bandwidth than with traditional TSVs. The larger TSV channels also have less resistance, deliver more power and offer lower latency, according to Intel. The advantage is that fewer vertical channels are required through the stacked die layers, leaving more space for transistors, for example.