IBM develops 2nm chip technology

IBM reports to have developed technology for 2nm chips. The company used its nanosheet technology for this. The announcement follows four years after that of 5nm chip technology, which was also based on nanosheets.

According to IBM, the 2nm technology enables 50 billion transistors on a chip “the size of a fingernail”, about 1.5 square centimeters. The company expects chips based on the technology to offer 45 percent higher performance than 7nm variants or consume 75 percent less energy.

IBM uses stacked gate-all-around transistors, which the company builds with layers it calls nanosheets. By using EUV patterning in manufacturing, IBM could produce nanosheets with widths from 15 to 70nm. IBM has already applied the 2nm technology to a chip. Cells of three stacked gaa transistors in that implementation have a height of 75nm and a width of 40nm with a gate length of 12nm. IBM does not disclose what kind of chip it is and what it will be used for, but the company does report that it is in the process of using 7nm technology for its Power10 chips for IBM Power Systems.

IBM is not the only party working on gate-all-around transistors as a successor to finfet transistors. Intel is developing these as part of its nanoribbon technology. Samsung wants to use GAa transistors for its 3nm node, but TSMC still uses finfet transistors for its 3nm process. In gate-all-around, the gate completely encloses the channel of field-effect transistors. In 2017, IBM announced its 5nm technology based on gaa, which it co-developed with Samsung and GlobalFoundries. The latter party stopped the development of 5nm and smaller by the way.