Espressif is working on WiFi-soc based on RISC-V

The Chinese manufacturer Espressif is working on a variant of the popular ESP32 WiFi controller, but with a CPU based on RISC-V instead of Xtensa. The controller seems to become pin compatible with the ESP8266.

The ESP32-C3 contains a single 32bit core based on the RISC-V architecture and with a clock speed of 160MHz. The controller supports WiFi and Bluetooth LE 5.0. This is evident from information from Espressif, including a datasheet, which has been listed by CNX. It is unclear whether Espressif released the information in China itself.

The soc contains 400KB sram and 384KB rom. This is a variant of the ESP32, which has one or two LX6 cores based on Cadence’s Xtensa architecture. The C3 variant of the ESP32 is pin compatible with the ESP8266. This is an older Wi-Fi controller from Espressif that has to do without Bluetooth support and is also less powerful than the ESP32. The ESP8266 also has an Xtensa core.

Espressif’s Wi-Fi controllers are popular for hobby projects because of their low price. By choosing RISC-V, Espressif no longer has to pay license costs to Cadence. RISC-V is an open source instruction set architecture that aims to make CPU designs freely available under a BSD license.