ARM introduces Cortex-A32 soc for wearables

ARM has presented a soc design for an ARMv8 Cortex-A32 intended to use only 4mW at 100MHz. The chip has been developed for ultra-low-power applications and embedded systems, such as wearables.

The chipset uses the new ARMv8 instruction set. It replaces the older A7 and A5 architectures, which use the ARMv7 instruction set. The Cortex A32 can only handle 32-bit code. This is because the ability to use 64-bit code has been removed to save space and energy. This makes it the first soc from ARM with the ARMv8 instruction set that does not support 64bit.

Despite the lack of 64-bit support, the new instruction set does deliver better performance in cryptographic calculations, Ars Technica writes. For 64bit support and also very low power consumption, ARM has the Cortex-A35 in its portfolio which uses up to 6mW at 100MHz.

According to ARM, Cortex-A32 is 25 percent more efficient than the Cortex-A7, while using less energy. A four core configuration of the Cortex-A32 at 1GHz would use less than 75mW per core and no more than 300mW in total.