‘Hynix is working on stacked memory with bandwidths up to 256GB/s’
Slides that appear to be from Hynix indicate that the company is working on a stacked-memory design for dram memory that could increase bandwidth to 256GB/s in the second generation. The ‘stacked memory’ is placed in the same place as the processor.
The Hynix slides describing a vertically stacked dram design under the heading of high-bandwidth memory have been published on Reddit, among others. With this design, the working memory would have a significantly larger bandwidth and the memory can be placed next to a processor on the same die. High-bandwidth memory would also be more energy efficient as a successor to the current ddr4, gddr5 and lpddr4 memory technology.
Hynix is collaborating with AMD on the technology, among others. In the first generation of stacked memory, four dram-dies are stacked on top of each other and these layers are connected to each other via vertical through-silicon via or TSV channels, which rest on a base layer. TSVs form paths through the silicon, as the name implies, thus ensuring short lines. With current packages with stacked chips, the interconnections run outside, and those longer paths result in losses in energy, bandwidth and costs. The basic die with I/O circuits is connected to, for example, the SOC via an underlying interposer, with the interposer serving as the underlying substrate and heat sink.
Based on the design Hynix is working on, a memory bandwidth of 128GB/s would be possible, significantly higher than current dram memory types. In a second generation of HBM chip designs, Hynix would like to double the speed through further scaling, to arrive at 256GB/s.
The first hbm designs could provide 4GB of RAM by stacking four 1GB dram slices. An 8GB design would also be feasible, but possibly due to limitations on the base layer design, this would not double the bandwidth.
It is still unclear when AMD will implement the memory technology developed with Hynix in chips. There are rumors that AMD will release Volcanic Island 2.0 GPUs using stacked dram in the second half of 2014, but other rumors suggest that AMD’s forthcoming Carrizo apu, which is to replace the Kaveri, has integrated stacked memory.