SK Hynix starts production of ‘4d nand’ based on periphery under cell technology

SK Hynix has announced 96-layer 512Gbit nand memory that the company dubs ‘4d nand’. The company combines 3d-nand with periphery under cell technology. Mass production is due to start this year.

For the new memory type, SK Hynix integrates its 3d-nand based on charge trap flash with periphery under cell. According to the company, a resulting 512Gbit chip with the 96-layer nand memory is 30 percent smaller than a 512Gbit chip with 72-layer 3d-nand. The new memory also has 30 percent faster write speeds and 25 percent higher read performance, according to SK Hynix. The claimed I/O speed is 1200Mbit/s at a voltage of 1.2V.

Periphery under cell is the name that SK Hynix uses for the technique to place the control logic of the memory cells under the nand. Since this logic no longer takes up precious die space in ‘the periphery’ of the cells, more cells can be placed and the density increases.

Image courtesy of Tom’s Hardware

That technique is not new. Intel and Micron are already using this for their 3d-nand, under the name cmos under array. However, those manufacturers use floating gates for their 3d-nand, so SK Hynix can claim to be the first company to combine charge trap flash with the technology. Incidentally, Samsung has also announced its own variant of cmos under array, writes Tom’s Hardware, which was present at the Flash Memory Summit in August, where SK Hynix gave a presentation about its ‘4d nand’.

SK Hynix reports that the 512Gbit chips could lead to the introduction of consumer SSDs with a storage capacity of 1TB this year, with the manufacturer using its own controllers and firmware. Business SSDs will follow next year and the company also expects to be able to produce 96-layer 1Tbit chips from Tlc and Qlc Nand.